Hot Interconnects II Symposium Proceedings, Stanford, CA, August 11-12, 1994
We describe the design of a reduced complexity interface to an ATM-based gigabit network, and present interim performance results. We describe how a simple yet high-performance interface can be implemented through the close coupling of hardware design and device driver development.
To put our work in perspective, we explore the trade-offs between host interface complexity and processing power. We look in particular at one complex ATM function, segmentation and reassembly (SAR) processing, and describe various approaches.
